1. Field of the Invention
The present invention relates to a semiconductor device for high-speed operation and, particularly, to a structure of the gate region for enhancing the performance of a MOSFET.
2. Discussion of Related Art
Some conventional MOS structures have a lightly doped LDD region to prevent deterioration of the structures' reliability due to the hot carrier effect, which is caused by high electric field at the edge of the drain. However, as the demand for high-speed operation increases, the concentration of dopants used in the LDD region also increases. As a result, the electric field at the edge of the gate increases, which tends to intensify the hot carrier effect.
One prior method used to counteract the problem involves gate poly oxidation (GPOX), which is partial oxidation in the vicinity of the edge of the gate. This partial oxidation tends to reduce the electric field near the edge of the gate, with a consequent reduction in the hot carrier effect. This method has been widely used for the gate structures of MOSFETs, attaining the above advantage in regard to the hot carrier effect. However, the increase in the size of the oxidation layer can cause a reduction in the speed of operation of the resulting device.
FIG. 1 contains a schematic cross-sectional diagram of a prior art MOSFET structure which is fabricated using a GPOX step. The structure is subjected to formation of a gate poly pattern to form the gate 3 of the device and then to a subsequent GPOX step. The GPOX step changes the thickness of the gate oxide layer 2 at the edge of the gate poly 3, which results in the formation of a thickened "bird's beak" region 10 at the edge of the gate oxide 2. This thickened region 10 extends into the channel region of the device at each side of the channel a distance of approximately 50 nm from the edge of the gate poly 3. Such a structure can reduce the hot carrier effect for a long MOSFET channel device but, in case of a short channel, such as those found in submicron devices, adversely affects the high-speed performance properties of the device because of a resulting reduction in the drain saturation current I.sub.dsat.
The prior art MOSFET structure as shown in FIG. 1 is manufactured by the following process. The gate oxide layer 2 is formed on a p-type silicon wafer 1, followed by a deposition of polysilicon on the gate oxide layer 2. The polysilicon layer is patterned by use of a gate pattern mask (not shown) to form a gate poly 3. The resulting structure is then subjected to the gate poly oxidation (GPOX) step, which forms an oxide layer having a thickness in the range of 7 to 17 nm. The gate oxide layer 2 is much thicker at the edge of the gate poly 3, resulting in the relatively thick bird's beak region 10.
Following formation of an n.sup.- region 4 by a subsequent LDD ion-implantation step, sidewalls 5 are formed on both sides of the gate poly 3. An n.sup.+ region is formed by a second ion-implantation such that the source and drain regions 6 of the LDD structure are completed. Hence, as shown in the drawing of FIG. 1, each thickened region 10 extends into the channel region of the device past the edge of the LDD region 6 approximately half of the distance that it extends from the edge of the gate poly 3, which in the illustrated structure is approximately 25 nm.
In the conventional GPOX process, the structure is subjected to heat treatment in a furnace to form an oxide layer region at the edge of the gate that is much thicker than the remainder of the gate oxide layer. During this oxidation step, the oxidant source, e.g., H.sub.2 O.sub.2, is diffused from the edge to the center of the gate poly along the interfaces between the gate poly 3 and the gate oxide layer 2. Oxidant diffusion also takes place between the gate oxide layer 2 and the silicon bulk. The result of this diffusion is formation of the relatively thick oxide region 10 which impairs the drain saturation current of the MOS device and consequently inhibits high-speed operation.
Hence, the conventional GPOX process reduces the hot carrier effect but also results in the thickened oxide region 10 formed deep under the lateral side of the gate, which causes a deterioration of the MOS device's properties, decreases the drain saturation current, and thereby hinders the high-speed driving of the circuit.